1. Field of the Invention
The present invention relates to a test method of measuring a disturbance value and a disturbance margin that are caused when a program disturbance stress is applied to a semiconductor non-volatile memory comprising a plurality of memory cells each having a gate, a floating gate, a drain, and a source.
2. Description of the Prior Art
A flash memory is one of such semiconductor non-volatile memories having a floating gate. A structural example of a semiconductor non-volatile memory is shown in FIG. 15. FIG. 15 shows a simplified cross-sectional view of the semiconductor non-volatile memory. This memory cell has a gate 1 having a control terminal 11, a floating gate 2, a drain 3 having a drain terminal 13, and a source 4 having a source terminal 14. A tunnel oxide layer 6 is formed between a substrate 5 and the floating gate 2.
A memory cell 21 shown in FIG. 15 takes either of two statuses, a programmed status (xe2x80x9c1xe2x80x9d) or an erased status (xe2x80x9c0xe2x80x9d) depending on an amount of charge stored in the floating gate 2. For example, when a channel formed between the drain 3 and the source 4 becomes non-conductive, the status of the memory cell is defined as xe2x80x9c0xe2x80x9d, and as xe2x80x9c1xe2x80x9d when the channel becomes conductive. In this way, the memory cell can hold and provide two-level data depending on the amount of charge stored in the floating gate 2.
By applying, for example, a positive voltage to the control terminal 11, and a negative voltage to the substrate 5, the drain terminal 13, and the source terminal 14, electrons are injected from the channel formed between the drain 3 and the source 4 into the floating gate 2 by a phenomenon called Fowler-Nordheim tunnel effect (hereinafter referred to as FN tunnel effect). Thus, the data of the memory cell is set to xe2x80x9c0xe2x80x9d. Under this condition, the negative charge stored in the floating gate 2 behaves like a barrier and prevents a current from flowing between the drain 3 and the source 4 even if a positive voltage is applied to the control terminal 11.
On the other hand, by applying, for example, a negative voltage to the control terminal 11 and a ground level to the substrate 5, and also by applying a positive voltage to the drain terminal 13, the negative charge that has been stored in the floating gate 2 is pulled out to the drain. Thus, the data of the memory cell is set to xe2x80x9c1xe2x80x9d. Under this condition, applying a positive voltage to the control terminal 11 allows a current to flow between the drain 3 and the source 4.
A memory cell array is composed of a plurality of such memory cells as described before. FIG. 16 shows an example of memory cell array circuit. A memory cell array 31 has six memory cells, 21a to 21f (hereinafter, these memory cells in FIG. 16 are collectively referred to as memory cell 21). The control terminal 11 of each memory cell is connected to a word line 32. Furthermore, the drain terminal 13 of one particular memory cell and the source terminal 14 of an adjacent memory cell are connected to a bit line 33. The memory cell array 31 is provided with seven bit lines, 33a to 33g (hereinafter, these bit lines in FIG. 16 are collectively referred to as bit line 33).
Before writing data to the memory cell array 31, memory cells should be erased by an injection of an excessive amount of negative charge into the floating gate 2 thereof. Then, for example, as shown in FIG. 16, a negative voltage xe2x88x92Vg is applied to the word line 32 to which each control terminal 11 of the memory cell 21 is connected. For example, if data xe2x80x9c0xe2x80x9d is written to the memory cell 21d, the bit line 33e connected to a drain terminal 13f thereof should be left floating (F), (hereinafter, all the drain terminals that are left floating are referred to as 13f). When, for example, writing data xe2x80x9c1xe2x80x9d to the memory cell 21b, the positive voltage +Vd is applied to the bit line 33c to which the drain terminal 13 thereof is connected.
When writing data xe2x80x9c0xe2x80x9d, the negative charge does not move from a floating gate 2f (hereinafter, the floating gate storing the negative charge is referred to as 2f) to the drain because the drain terminal 13f is left floating, and therefore a sufficiently high electric field to initiate the FN tunnel effect will not be generated in the tunnel oxide layer 6. On the other hand, when writing data xe2x80x9c1xe2x80x9d, the negative charge moves from the floating gate 2 to the drain because the positive voltage +Vd is applied to the drain terminal 13 generating a sufficiently high electric field to initiate the FN tunnel effect in the tunnel oxide layer 6. In this way, data xe2x80x9c1xe2x80x9d is written to the memory cell.
Individual memory cells that altogether constitute a memory cell array are not uniform in properties because of manufacturing variations or the like. When writing to memory cells (programming), as described before, the negative voltage xe2x88x92Vg is applied as a stress voltage through a word line to the control terminal of the memory cell that is supposed to be written to xe2x80x9c0xe2x80x9d. Considering these factors, if a plurality of memory cells sharing an identical word line have a fairly large amount of variations in properties, some memory cells may switch from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d when the negative charge stored in the floating gate thereof moves to the drain initiated by the FN tunnel effect despite that the bit line thereof is left floating. In this way, the stress voltage may cause a threshold voltage to decline.
It is, therefore, extremely important to measure the amount of disturbance received by each memory cell that altogether constitutes a memory cell array. In constructing a test program algorithm, it is also important to measure a disturbance margin which is an indication of margin between the algorithm of the test program and the actual memory cells to be tested. These values can be also utilized as criteria during an outgoing inspection of products.
Measuring the program disturbance value and the disturbance margin that indicate an amount of disturbance when the memory cells are programmed, is an intrinsically necessary test regardless of types of flash memories. Specifically, if the polarity of writing voltage or the like is optimally adjusted, this test method can be employed for testing such flash memories as NOR, NAND, DINOR, virtual-ground NOR types, and the like regardless of types. Mentioned hereunder are examples of the conventional test methods for evaluating the amount of program disturbance on memory cells.
An extremely common evaluation method includes steps to apply to erased memory cells, a program disturbance stress that is equivalent to the one prescribed by specifications, then to read each memory cell, and to evaluate the result to see if the memory cells still maintain the erased status.
Another program disturbance stress test includes steps to apply to the erased memory cells, a program disturbance stress that is equivalent to the one prescribed by specifications or the like, then to evaluate whether or not the resultant threshold levels have exceeded the specified level or the like.
In order to conduct a more accurate test for the program disturbance margin, another test includes a first procedure to measure the time or the number of program pulse steps required for completing programming all the memory cells that undergo the programming operation simultaneously. In a second procedure, among identical memory cells, the time or the number of pulse steps required for the first memory cell to shift from the erased level to the programmed level after being stressed under the program disturbance will be measured. The results in terms of the time or the number of steps obtained through the above two procedures will be compared for evaluation.
However, the above-mentioned test methods have the following shortcomings. a Test method 1 is only effective for judging if some memory cells have caused a disturbance fault (a memory cell switching from the erased level to the programmed level unnecessarily under the stress) under the program disturbance stress. The shortcoming of this method, however, is that no information on the program disturbance margin can be obtained.
Test method 2 is effective in knowing whether or not the memory cells have the program disturbance margin that is prescribed by specifications or the like. The shortcoming of this method, however, is that the amount of margin itself can not be obtained.
Test method 3 is effective for making a quantitative evaluation on the program disturbance margin that has been prescribed by specifications or the like. However, it generally takes much longer time to cause a disturbance fault than to complete programming memory cells. As a result, the shortcoming of this test method is that it takes very long time to complete the test because the program disturbance stress should be kept applying until the actual disturbance fault is caused.
The Japanese Patent Application Laid-Open No. H9-91980 discloses methods for programming semiconductor non-volatile memories in two- or multiple-level by employing a linier curve relation between the voltage applied to the control terminal and the threshold value thereof. This document, however, does not disclose a test method for semiconductor non-volatile memories. Particularly, a test method for evaluating whether non-volatile memories are good or defective when the disturbance stress is applied to control terminals thereof is not disclosed.
An object of the present invention is to provide test methods for semiconductor non-volatile memories, thereby enabling disturbance values and disturbance margins to be tested and evaluated accurately in a shorter period of time.
To achieve the above object, according to one aspect of the present invention, a method of testing a semiconductor non-volatile memory comprising a plurality of memory cells each of which has a gate, a floating gate, a drain, and a source, includes:
a first step of applying, after erasing the memory cells, a program disturbance stress pulse train whose voltage changes in increments, to a word line to which the memory cells are connected, up to the voltage reaches a final voltage required to complete programming all the memory cells that share an identical word line and are subjected to an identical program disturbance stress simultaneously;
a second step of repeating the first step by changing word lines until a final word completed; and
a third step of measuring a lowest threshold value among the memory cells sharing an identical word line by changing word lines until the final word line is completed.
In the case of a semiconductor non-volatile memory, a disturbance value and a disturbance margin on each word line can be measured and evaluated simply by obtaining the lowest threshold voltage on each word line because the most disturbed memory cell among the memory cells sharing an identical word line has the lowest threshold value.
According to another aspect of the present invention, said program disturbance stress pulse train has incremental pulses wherein a ratio of a voltage increase to a pulse width is always constant.
Therefore, a difference between the lowest threshold value to maintain the erased level and the lowest threshold value obtained on each word line from the memory cells sharing the identical word line can translate directly into the program disturbance margin for the voltage applied to each word line. It also becomes possible to calculate the number of necessary test steps.
According to another aspect of the present invention, said semiconductor nonvolatile volatile memory has reference memory cells. When applying said program disturbance pulse train, a program pulse train is also applied to a drain terminal of the reference memory cell, wherein the program disturbance stress train is kept being applied up to the step in which the reference memory cell has been programmed or up to a specified step beyond the step in which the reference memory cell has been programmed.
By employing the reference memory cell, it becomes possible to conduct a concurrent test including the program test and the program disturbance test covering each word line voltage by which the reference memory cell completes programming.
In this case, a dedicated reference memory cell region may be provided outside the region in which all of the memory cells receive an identical program disturbance stress simultaneously. It is also possible to provide any given memory cell out of memory cells that receive an identical program disturbance stress simultaneously, as a reference memory cell. In this case, it becomes possible to conduct tests for the program disturbance value and the program disturbance margin without increasing a memory chip size.
According to another aspect of the present invention, said final voltage mentioned in the first aspect of the present invention, may be any given voltage within a step required to complete programming a plurality of memory cells that are connected to an identical word line and receive an identical program disturbance stress simultaneously.
It is, therefore, possible to shorten the time required for completing the test because the number of steps for applying the disturbance stress pulse is reduced for each word line than otherwise necessary.